The AD-FMCOMMS3-EBZ is a high-speed analog module designed to showcase the AD9361, a high performance, highly integrated RF transceiver intended for use in RF applications, such as 3G and 4G base station and test equipment applications, and software defined radios. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor or FPGA. The AD9361 chip operates in the 70 MHz to 6 GHz range, covering most licensed and unlicensed bands. The chip supports channel bandwidths from less than 200 kHz to 56 MHz by changing sample rate, digital filters, and decimation, which are all programmable within the AD9361 itself.
The AD-FMCOMMS3-EBZ provides software developers and system architect who want a single platform to operate over a wider tuning range than the AD-FMCOMMS2-EBZ. RF performance expectations of this board must be tempered with the very wide band front end. It does meet the datasheet specifications at 2.4 GHz, but does not over the entire RF tuning range that the board supports. Typical performance data for the entire range (70 MHz – 6 GHz) which is supported by the platform is published within the board documentation. This board is primarily intended for system investigation and bringing up various waveforms from a software team before custom hardware is complete. The objective being for designers to see waveforms, but not being concerned about the last 1dB or 1% EVM of performance. For performance-oriented platforms – please refer to the AD-FMCOMMS2-EBZ.
AD-FMCOMMS3-EBZ Product Features
- Software tunable across wide frequency range (70 MHz to 6.0 GHz) with a channel bandwidth of <200 kHz to 56 MHz.
- Phase and frequency synchronization on both transmit and receive paths
- Allows high channel density
- Powered from single FMC connector
- Supports MIMO radio, with less than 1 sample sync on both ADC and DAC
- Includes schematics, layout, BOM, HDL, Linux drivers and application software
- Supports add on cards for spectrum specific designs (PA, LNA, etc.)
FMCOMMS3-EBZ System Requirements
What you need, depends on what you are trying to do. As a minimum, you need to start out with:
The AD9361/AD9364 based card. To determine which card is best for you, check out the introduction section.
A carrier platform. ADI does not offer these boards for sale or loan, getting one yourself is normal part of development or evaluation of the AD9361/AD9364. Our recommended carriers (the ones we use all the time) are either:
The ZedBoard. This is a low cost board, which can be used for basic HDL designs, or just for looking at the AD9361/AD9364. Most of our software and RF developers have this board.
The Xilinx ZC706. The fabric on this device is much larger, and if you are looking at targeting – this is the recommended option.
The Arrow SoCKit. This is a low cost board, which can be used for basic HDL designs, or just for looking at the AD9361.
There are a few more boards, which do work, and are supported, but they are just not tested as often (most of the full time developers who work with the AD9361/AD9364 based boards use the Zed or the ZC706). The experience of the fabric only solutions is very close to the ARM/FPGA SoC based solutions, but the GUI runs on a host PC (Windows or Linux).
The AD-FMCOMMS2/3/4/5-EBZ is, by definition a “FPGA mezzanine card” (FMC), that means it needs a carrier to plug into. The carriers we support are:
Board FMCOMMS5 FMCOMMS2/3/4 Arradio AC701 √ KC705 √ KCU105 √ VC707 √ ZC702 √ √ ZC706 √ √ ZCU102 √ √ Zed Board √ MITX045 √ SoCKit √
some way to interact with the platform,
Internet connection (without proxies makes things much easier) to update the scripts/binaries on the SD Card that came with the ADI FMC Card. (Firewalls are OK, proxies make things a pain).
RF Test equipment
ZedBoard™ is a complete development kit for designers interested in exploring designs using the Xilinx Zynq®-7000 All Programmable SoC. The board contains all the necessary interfaces and supporting functions to enable a wide range of applications. The expandability features of the board make it ideal for rapid prototyping and proof-of-concept development.
The AD9361 is a high performance, highly integrated radio frequency (RF) Agile Transceiver™ designed for use in 3G and 4G base station applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications.
The device combines a RF front end with a flexible mixed-signal baseband section and integrated frequency ynthesizers, simplifying design-in by providing a configurable digital interface to a processor.
The AD9361 receiver LO operates from 70 MHz to 6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 56 MHz are supported.
The two independent direct conversion receivers have state-of-theart noise figure and linearity. Each receive (RX) subsystem includes independent automatic gain control (AGC), dc offset correction, quadrature correction, and digital filtering, thereby eliminating the need for these functions in the digital baseband.
The AD9361 also has flexible manual gain modes that can be externally controlled. Two high dynamic range analog-to-digital converters (ADCs) per channel digitize the received I and Q signals and pass them through configurable decimation filters and 128-tap finite impulse response (FIR) filters to produce a 12-bit output signal at
the appropriate sample rate.
The transmitters use a direct conversion architecture that achieves high modulation accuracy with ultralow noise. This transmitter design produces a best in class TX error vector magnitude (EVM) of <−40 dB, allowing significant system margin for the external power amplifier (PA) selection. The on-board transmit (TX) power monitor can be used as a power detector, enabling highly accurate TX power measurements.
The fully integrated phase-locked loops (PLLs) provide low power fractional-N frequency synthesis for all receive and transmit channels. Channel isolation, demanded by frequency division duplex (FDD) systems, is integrated into the design.
All VCO and loop filter components are integrated. The core of the AD9361 can be powered directly from a 1.3 V
regulator. The IC is controlled via a standard 4-wire serial port and four real-time input/output control pins. Comprehensive power-down modes are included to minimize power consumption during normal use.
The AD9361 is packaged in a 10 mm × 10 mm, 144-ball chip scale package ball grid array (CSP_BGA).