# Reading pref.tcl
# //  Questa Intel Starter FPGA Edition-64
# //  Version 2021.2 win64 Apr 14 2021
# //
# //  Copyright 1991-2021 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# do test_uart_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Questa Intel Starter FPGA Edition-64 vmap 2021.2 Lib Mapping Utility 2021.04 Apr 14 2021
# vmap work rtl_work 
# Copying C:/intelFPGA_lite/21.1/questa_fse/win64/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+D:/class/uart {D:/class/uart/tx.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 11:21:38 on Feb 07,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart" D:/class/uart/tx.v 
# -- Compiling module tx
# 
# Top level modules:
# 	tx
# End time: 11:21:38 on Feb 07,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart {D:/class/uart/baud_rate_en.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 11:21:38 on Feb 07,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart" D:/class/uart/baud_rate_en.v 
# -- Compiling module baud_rate_en
# 
# Top level modules:
# 	baud_rate_en
# End time: 11:21:38 on Feb 07,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart {D:/class/uart/uart.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 11:21:39 on Feb 07,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart" D:/class/uart/uart.v 
# -- Compiling module uart
# 
# Top level modules:
# 	uart
# End time: 11:21:39 on Feb 07,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart {D:/class/uart/uart_pll.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 11:21:39 on Feb 07,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart" D:/class/uart/uart_pll.v 
# -- Compiling module uart_pll
# 
# Top level modules:
# 	uart_pll
# End time: 11:21:39 on Feb 07,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart {D:/class/uart/test_uart.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 11:21:39 on Feb 07,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart" D:/class/uart/test_uart.v 
# -- Compiling module test_uart
# 
# Top level modules:
# 	test_uart
# End time: 11:21:39 on Feb 07,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart/db {D:/class/uart/db/uart_pll_altpll.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 11:21:39 on Feb 07,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart/db" D:/class/uart/db/uart_pll_altpll.v 
# -- Compiling module uart_pll_altpll
# 
# Top level modules:
# 	uart_pll_altpll
# End time: 11:21:40 on Feb 07,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+D:/class/uart {D:/class/uart/tb.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 11:21:40 on Feb 07,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart" D:/class/uart/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 11:21:40 on Feb 07,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc"  tb
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" tb 
# Start time: 11:21:40 on Feb 07,2022
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vopt-143) Recognized 1 FSM in module "tx(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "test_uart(fast)".
# Loading work.tb(fast)
# Loading work.test_uart(fast)
# Loading work.uart(fast)
# Loading work.uart_pll(fast)
# Loading altera_mf_ver.altpll(fast)
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES(fast)
# Loading altera_mf_ver.MF_cycloneiii_pll(fast)
# Loading altera_mf_ver.cda_m_cntr(fast)
# Loading altera_mf_ver.cda_n_cntr(fast)
# Loading altera_mf_ver.cda_scale_cntr(fast)
# Loading altera_mf_ver.pll_iobuf(fast)
# Loading work.baud_rate_en(fast)
# Loading work.tx(fast)
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 80000  Instance: tb.test_uart_inst.uart_inst.uart_pll_inst.altpll_component.cycloneiii_pll.pll3
# Causality operation skipped due to absence of debug database file
add wave -position insertpoint sim:/tb/test_uart_inst/*
restart
# ** Note: (vsim-8009) Loading existing optimized design _opt
# Loading work.tb(fast)
# Loading work.test_uart(fast)
# Loading work.uart(fast)
# Loading work.uart_pll(fast)
# Loading altera_mf_ver.altpll(fast)
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES(fast)
# Loading altera_mf_ver.MF_cycloneiii_pll(fast)
# Loading altera_mf_ver.cda_m_cntr(fast)
# Loading altera_mf_ver.cda_n_cntr(fast)
# Loading altera_mf_ver.cda_scale_cntr(fast)
# Loading altera_mf_ver.pll_iobuf(fast)
# Loading work.baud_rate_en(fast)
# Loading work.tx(fast)
run -all
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 80000  Instance: tb.test_uart_inst.uart_inst.uart_pll_inst.altpll_component.cycloneiii_pll.pll3
run -continue
run -all
run -all
# End time: 11:27:04 on Feb 07,2022, Elapsed time: 0:05:24
# Errors: 0, Warnings: 0
