Xilinx and Altera Risc-V FPGA Board, Risc-V FPGA Boards, Risc-V Learning Boards – Step by Step teaching you how to code in RISC-V machine
Risc-V Board One: FII-PRX100 Development Board ARTIX 100T, XC7A100T – Xinlix FPGA Board.
FII-PRX100 RISC-V development board
- Suitable for FPGA study and training
- Fully support FIE310 CPU running and system development
- Suitable for user customized RV32G verification and validation
- JTAG interface for FPGA and FIE310 CPU download and debug
- Support Windows software and linux development environment
- GCC compilation toolchain and graphical software development environment
- Hardware resource: Switchs, Push Button ,USB to UART convertor, QSPI flash, I2C EEPROM, 100M/1G ethernet, USB keyboard mouse,GPIO , hdmi transmitter and camera etc.
System Design Objective
The main purpose of this system design is to complete FPGA learning, development and experiment with Xilin-Vivado. The main device uses the Xilinx-XC7A100T-2FGG676I and is currently the latest generation of FPGA devices from Xilinx. The main learning and development projects can be completed as follows:
- Basic FPGA design training
- Construction and training of the SOPC (Microblaze) system
- IC design and verification, the system provides hardware design, simulation and verification of RISC-V CPU
- Development and application based on RISC-V
- The system is specifically optimized for hardware design for RISC-V system applications
2. System Resource
- Extended memory
- Use two Super Srams in parallel to form a 32-bit data interface with a maximum access space of 2M bytes.
- IS61WV51216 (2 pieces) 512K x 32bit
- Serial flash
- Spi interface serial flash (128M bytes)
- Serial EEPROM
- Gigabit Ethernet: 100/1000 Mbps
- USB to serial interface: USB-UART bridge
3. Human-computer Interaction Interface
- 8 toggle switches
- 8 push buttons
- Definition of 7 push buttons: up, down, left, right, ok, menu, return
- 1 for rest: Reset button
- 8 LEDs
- 6 7-segment decoders
- I2C bus interface
- UART external interface
- Two JTAG programming interfaces
- One is for downloading the FPGA debug interface, and the other one is the JTAG debug interface for the RISC-V CPU
- Built-in RISC-V
- CPU software debugger, no external RISC-V JTAG emulator required
- 12-pin GIPIO connectors, in line with PMOD interface standards
4 Software Development System
- Vivado 18.1 and later version for FPGA development, Microblaze SOPC
- Freedom Studio-Win_x86_64 Software development for RISC-V CPU
5. Supporting Resources
- RISC-V JTAG Debugger
- xilinx Altera JTAG Download Debugger
- FII-PRX100 Development Guide
What Risc-V FPGA Board can be used for ?
RISC–V, pronounced ‘Risk-Five’, is a new architecture that’s available under open, free and non-restrictive licences. It has widespread industry support from chip and device makers, and is designed to be freely extensible and customisable to fit any market niche.
The RISC-V hardware instruction set architecture is unique, in that it’s a modern architecture that’s both open source and useful in the real world. But, it was mostly developed with embedded processing solutions in mind, such as for IoT applications or edge computing.
Of course, that doesn’t mean there isn’t any interest in a RISC-V PC, and so this team developed one that can run Fedora Linux with the help of an FPGA for the peripherals.