复杂数字钟设计（7）–模块组装及硬件调试(PRX100-D)

经过前面几个步骤的分析与设计，目前对于各个模块的抽象，封装以及各个模块之间接口与功能的划分已经非常清晰，把修改后的功能框图以及顶层的源代码重新呈现给大家。根据这两部分内容并结合PRX100-D硬件原理图组织硬件实验与调试。

图1

1.模块组装

在Vivado下新建工程见文章Vivado软件的使用。移植复杂数字钟工程到Vivado需要注意以下几点：

仔细阅读硬件原理图，正确分配管脚，写入到*.xdc文件中。（PRA006和PRX100-D上按键的逻辑正好相反，详细见下图3。）
注意电平的兼容性
IP核需要重新生成及例化

module complex_counter
(
input inclk,
input sw_in_l, sw_in_r, sw_in_p, sw_in_m,
output [ 5: 0 ] SEAT,
output DP,
output [ 6: 0 ] SEVEN_SEG
);
wire pll_locked;
wire sys_clk;
wire rst = !pll_locked;
wire ms_p;
wire s_p;
wire [ 3: 0 ] s_l;
wire [ 3: 0 ] s_h;
wire [ 3: 0 ] m_l;
wire [ 3: 0 ] m_h;
wire [ 3: 0 ] h_l;
wire [ 3: 0 ] h_h;
wire [ 3: 0 ] d_l;
wire [ 3: 0 ] d_h;
wire [ 3: 0 ] mh_l;
wire [ 3: 0 ] mh_h;
wire [ 5: 0 ] dp_tmp;
wire [ 3: 0 ] seg_a;
wire [ 3: 0 ] seg_b;
wire [ 3: 0 ] seg_c;
wire [ 3: 0 ] seg_d;
wire [ 3: 0 ] seg_e;
wire [ 3: 0 ] seg_f;
wire sw_l;
wire sw_r;
wire sw_p;
wire sw_m;
wire [ 9: 0 ] dp_pos;
f_div f_div_inst
(
.rst  ( rst ),
.clk  ( sys_clk ),
.ms_p ( ms_p ),
.s_p  ( s_p )
);
sw_debounce sw_debounce_inst
(
.rst        ( rst ),
.clk        ( sys_clk ),
.ms_p       ( ms_p ),
.sw_in_l    ( sw_in_l ),
.sw_in_r    ( sw_in_r ),
.sw_in_p    ( sw_in_p ),
.sw_in_m    ( sw_in_m ),
.sw_out_l   ( sw_l ),
.sw_out_r   ( sw_r ),
.sw_out_p   ( sw_p ),
.sw_out_m   ( sw_m )
);
count count_inst
(
.rst        ( rst ),
.clk        ( sys_clk ),
.s_p        ( s_p ),
.sw_in_l    ( sw_l ),
.sw_in_r    ( sw_r ),
.sw_in_p    ( sw_p ),
.sw_in_m    ( sw_m ),
.s_out_l    ( s_l ),
.s_out_h    ( s_h ),
.m_out_l    ( m_l ),
.m_out_h    ( m_h ),
.h_out_l    ( h_l ),
.h_out_h    ( h_h ),
.d_out_l    ( d_l ),
.d_out_h    ( d_h ),
.mh_out_l   ( mh_l ),
.mh_out_h   ( mh_h ),
.dp_out_pos ( dp_pos )
);
schdl_adjust schdl_adjust_inst
(
.rst        ( rst ),
.clk        ( sys_clk ),
.s_p        ( s_p ),
.dp_in_pos  ( dp_pos ),
.s_in_l     ( s_l ),
.s_in_h     ( s_h ),
.m_in_l     ( m_l ),
.m_in_h     ( m_h ),
.h_in_l     ( h_l ),
.h_in_h     ( h_h ),
.d_in_l     ( d_l ),
.d_in_h     ( d_h ),
.mh_in_l    ( mh_l ),
.mh_in_h    ( mh_h ),
.dp_out     ( dp_tmp ),
.seg_out_a  ( seg_a ),
.seg_out_b  ( seg_b ),
.seg_out_c  ( seg_c ),
.seg_out_d  ( seg_d ),
.seg_out_e  ( seg_e ),
.seg_out_f  ( seg_f )
);
scan_dis_7seg scan_dis_7seg_inst
(
.rst        ( rst ),
.clk        ( sys_clk ),
.ms_p       ( ms_p ),
.seg_in_a   ( seg_a ),
.seg_in_b   ( seg_b ),
.seg_in_c   ( seg_c ),
.seg_in_d   ( seg_d ),
.seg_in_e   ( seg_e ),
.seg_in_f   ( seg_f ),
.dp_in      ( dp_tmp ),
.SEAT       ( SEAT ),
.DP         ( DP ),
.seven_seg  ( SEVEN_SEG )
);
pll1 pll1_inst
(
.areset     ( 1'b0 ),
.inclk0     ( inclk ),
.c0         ( sys_clk ),
.locked     ( pll_locked )
);
endmodule

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module complex_counter

(

input inclk,

input sw_in_l, sw_in_r, sw_in_p, sw_in_m,

output [ 5: 0 ] SEAT,

output DP,

output [ 6: 0 ] SEVEN_SEG

);

wire pll_locked;

wire sys_clk;

wire rst = !pll_locked;

wire ms_p;

wire s_p;

wire [ 3: 0 ] s_l;

wire [ 3: 0 ] s_h;

wire [ 3: 0 ] m_l;

wire [ 3: 0 ] m_h;

wire [ 3: 0 ] h_l;

wire [ 3: 0 ] h_h;

wire [ 3: 0 ] d_l;

wire [ 3: 0 ] d_h;

wire [ 3: 0 ] mh_l;

wire [ 3: 0 ] mh_h;

wire [ 5: 0 ] dp_tmp;

wire [ 3: 0 ] seg_a;

wire [ 3: 0 ] seg_b;

wire [ 3: 0 ] seg_c;

wire [ 3: 0 ] seg_d;

wire [ 3: 0 ] seg_e;

wire [ 3: 0 ] seg_f;

wire sw_l;

wire sw_r;

wire sw_p;

wire sw_m;

wire [ 9: 0 ] dp_pos;

f_div f_div_inst

(

.rst ( rst ),

.clk ( sys_clk ),

.ms_p ( ms_p ),

.s_p ( s_p )

);

sw_debounce sw_debounce_inst

(

.rst ( rst ),

.clk ( sys_clk ),

.ms_p ( ms_p ),

.sw_in_l ( sw_in_l ),

.sw_in_r ( sw_in_r ),

.sw_in_p ( sw_in_p ),

.sw_in_m ( sw_in_m ),

.sw_out_l ( sw_l ),

.sw_out_r ( sw_r ),

.sw_out_p ( sw_p ),

.sw_out_m ( sw_m )

);

count count_inst

(

.rst ( rst ),

.clk ( sys_clk ),

.s_p ( s_p ),

.sw_in_l ( sw_l ),

.sw_in_r ( sw_r ),

.sw_in_p ( sw_p ),

.sw_in_m ( sw_m ),

.s_out_l ( s_l ),

.s_out_h ( s_h ),

.m_out_l ( m_l ),

.m_out_h ( m_h ),

.h_out_l ( h_l ),

.h_out_h ( h_h ),

.d_out_l ( d_l ),

.d_out_h ( d_h ),

.mh_out_l ( mh_l ),

.mh_out_h ( mh_h ),

.dp_out_pos ( dp_pos )

);

schdl_adjust schdl_adjust_inst

(

.rst ( rst ),

.clk ( sys_clk ),

.s_p ( s_p ),

.dp_in_pos ( dp_pos ),

.s_in_l ( s_l ),

.s_in_h ( s_h ),

.m_in_l ( m_l ),

.m_in_h ( m_h ),

.h_in_l ( h_l ),

.h_in_h ( h_h ),

.d_in_l ( d_l ),

.d_in_h ( d_h ),

.mh_in_l ( mh_l ),

.mh_in_h ( mh_h ),

.dp_out ( dp_tmp ),

.seg_out_a ( seg_a ),

.seg_out_b ( seg_b ),

.seg_out_c ( seg_c ),

.seg_out_d ( seg_d ),

.seg_out_e ( seg_e ),

.seg_out_f ( seg_f )

);

scan_dis_7seg scan_dis_7seg_inst

(

.rst ( rst ),

.clk ( sys_clk ),

.ms_p ( ms_p ),

.seg_in_a ( seg_a ),

.seg_in_b ( seg_b ),

.seg_in_c ( seg_c ),

.seg_in_d ( seg_d ),

.seg_in_e ( seg_e ),

.seg_in_f ( seg_f ),

.dp_in ( dp_tmp ),

.SEAT ( SEAT ),

.DP ( DP ),

.seven_seg ( SEVEN_SEG )

);

pll1 pll1_inst

(

.areset ( 1'b0 ),

.inclk0 ( inclk ),

.c0 ( sys_clk ),

.locked ( pll_locked )

);

endmodule

2.开发板FII-PRX100-D资源的使用

- 数码管，如图2

图2

按键资源

图3

资源与FPGA管脚映射，如表1，

顶层module信号名	网络标号	FPGA管脚	开发板上的标识	FPGA管脚电平瞄准	端口说明
inclk	C10_50MCLK	D18		LVCMOS33	输入时钟
sw_in_p	KEY2	L4	PB0	LVCMOS33	按键(+)
sw_in_m	KEY7	R7	PB3	LVCMOS33	按键（-）
sw_in_l	KEY4	K5	PB1	LVCMOS33	按键左移
sw_in_r	KEY6	P1	PB2	LVCMOS33	按键右移
SEAT[5]	SEG_3V3_D5	R16		LVCMOS33	位选信号第5位
SEAT[4]	SEG_3V3_D4	R17		LVCMOS33	位选信号第4位
SEAT[3]	SEG_3V3_D3	N18		LVCMOS33	位选信号第3位
SEAT[2]	SEG_3V3_D2	K25		LVCMOS33	位选信号第2位
SEAT[1]	SEG_3V3_D1	R25		LVCMOS33	位选信号第1位
SEAT[0]	SEG_3V3_D0	P21		LVCMOS33	位选信号第0位
SEVEN_SEG[6]	SEG_PG	P23		LVCMOS33	段选信号第7位
SEVEN_SEG[5]	SEG_PF	T24		LVCMOS33	段选信号第6位
SEVEN_SEG[4]	SEG_PE	N22		LVCMOS33	段选信号第5位
SEVEN_SEG[3]	SEG_PD	N21		LVCMOS33	段选信号第4位
SEVEN_SEG[2]	SEG_PC	L20		LVCMOS33	段选信号第3位
SEVEN_SEG[1]	SEG_PB	M20		LVCMOS33	段选信号第2位
SEVEN_SEG[0]	SEG_PA	K26		LVCMOS33	段选信号第1位
DP	SEG_DP	P24		LVCMOS33	小数点

在工程中锁定管脚

Vivado的管脚约束文件如下：

####################################################################################
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports inclk]
create_clock -period 20.000 -name inclk -waveform {0.000 10.000} [get_ports inclk]
####################################################################################
set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports sw_in_p]
set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports sw_in_l]
set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports sw_in_r]
set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports sw_in_m]
set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS33} [get_ports {SEVEN_SEG[0]}]
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {SEVEN_SEG[1]}]
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports {SEVEN_SEG[2]}]
set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS33} [get_ports {SEVEN_SEG[3]}]
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33} [get_ports {SEVEN_SEG[4]}]
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS33} [get_ports {SEVEN_SEG[5]}]
set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports {SEVEN_SEG[6]}]
set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVCMOS33} [get_ports DP]
set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {SEAT[5]}]
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {SEAT[4]}]
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports {SEAT[3]}]
set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS33} [get_ports {SEAT[2]}]
set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS33} [get_ports {SEAT[1]}]
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports {SEAT[0]}]

####################################################################################

set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports inclk]

create_clock -period 20.000 -name inclk -waveform {0.000 10.000} [get_ports inclk]

####################################################################################

set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports sw_in_p]

set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports sw_in_l]

set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports sw_in_r]

set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports sw_in_m]

set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS33} [get_ports {SEVEN_SEG[0]}]

set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {SEVEN_SEG[1]}]

set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports {SEVEN_SEG[2]}]

set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS33} [get_ports {SEVEN_SEG[3]}]

set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33} [get_ports {SEVEN_SEG[4]}]

set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS33} [get_ports {SEVEN_SEG[5]}]

set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports {SEVEN_SEG[6]}]

set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVCMOS33} [get_ports DP]

set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {SEAT[5]}]

set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {SEAT[4]}]

set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports {SEAT[3]}]

set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS33} [get_ports {SEAT[2]}]

set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS33} [get_ports {SEAT[1]}]

set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports {SEAT[0]}]

重新编译complex_counter 工程并下载，调试。

扩展设计：

添加年份计数及显示。
添加闰年计算，调整2月的天数。
添加蜂鸣器，实现整点报时（PRX100-D），蜂鸣器的使用请参照蜂鸣器实验。

复杂数字钟设计（7）–模块组装及硬件调试(PRX100-D)

1.模块组装

2.开发板FII-PRX100-D资源的使用

重新编译complex_counter 工程并下载，调试。

芯片类文章

计算机语言教程

芯片设计

百科关键词

复杂数字钟设计（7）–模块组装及硬件调试(PRX100-D)

1.模块组装

2.开发板FII-PRX100-D资源的使用

重新编译complex_counter 工程并下载，调试。

相关文章：

芯片类文章

计算机语言教程

芯片设计

百科关键词

文章关键词