互联网MAC层CRC32 生成器

// Module Name: eth_mac_rx
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 互联网MAC层 CRC32 生成器 Verilog 代码
//////////////////////////////////////////////////////////////////////////////////
module CRC_gen 
(
input           clk,
input           init,
input   [7:0]   frame_data,
input           data_en,
input           crc_rd ,
output  [7:0]   crc_out,
output          crc_end,
input           rst
);
//=======================================================================   
//internal signals                                                              
//=======================================================================   
reg [7:0]       crc_out;
reg [31:0]      crc_reg;
reg             crc_end;
reg [3:0]       counter;
//=======================================================================   
//input data width is 8bit, and the first bit is bit[0]
function [31:0]  NextCRC;
input [7:0]  D;
input [31:0] C;
reg [31:0]   NewCRC;
begin
NewCRC[0] = C[24]^C[30]^D[1]^D[7];
NewCRC[1] = C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[2] = C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[3] = C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[4] = C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
NewCRC[5] = C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[6] = C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[7] = C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[8] = C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[9] = C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
NewCRC[10] = C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[11] = C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[12] = C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[13] = C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[14] = C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
NewCRC[15] = C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
NewCRC[16] = C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
NewCRC[17] = C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
NewCRC[18] = C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
NewCRC[19] = C[11]^C[31]^D[0]^C[27]^D[4];
NewCRC[20] = C[12]^C[28]^D[3];
NewCRC[21] = C[13]^C[29]^D[2];
NewCRC[22] = C[14]^C[24]^D[7];
NewCRC[23] = C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[24] = C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[25] = C[17]^C[27]^D[4]^C[26]^D[5];
NewCRC[26] = C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
NewCRC[27] = C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
NewCRC[28] = C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
NewCRC[29] = C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
NewCRC[30] = C[22]^C[31]^D[0]^C[28]^D[3];
NewCRC[31] = C[23]^C[29]^D[2];
NextCRC = NewCRC;
end
endfunction
//=======================================================================   
always @ (posedge clk or posedge rst)
if (rst)            crc_reg &lt;= 32'hffffffff;
else if (init)      crc_reg &lt;= 32'hffffffff;
else if (data_en)   crc_reg &lt;= NextCRC(frame_data,crc_reg);
else if (crc_rd)    crc_reg &lt;= {crc_reg[23:0],8'hff};
always @ (crc_rd or crc_reg)
if (crc_rd)
crc_out &lt;= ~{crc_reg[24],crc_reg[25],crc_reg[26],crc_reg[27],crc_reg[28],crc_reg[29],crc_reg[30],crc_reg[31]};
else
crc_out &lt;= 0;
//caculate CRC out length ,4 cycles     
//CRC_end aligned to last CRC checksum data
always @(posedge clk or posedge rst)
if (rst)    counter &lt;= 0;
else if (!crc_rd)    counter &lt;= 0;
else     counter &lt;= counter + 1;
always @ (counter)
if (counter == 3) crc_end = 1;
else crc_end = 0;
//=======================================================================   
endmodule

100

101

102

103

// Module Name: eth_mac_rx

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

// 互联网MAC层 CRC32 生成器 Verilog 代码

//////////////////////////////////////////////////////////////////////////////////

module CRC_gen

(

input clk,

input init,

input [7:0] frame_data,

input data_en,

input crc_rd ,

output [7:0] crc_out,

output crc_end,

input rst

);

//=======================================================================

//internal signals

//=======================================================================

reg [7:0] crc_out;

reg [31:0] crc_reg;

reg crc_end;

reg [3:0] counter;

//=======================================================================

//input data width is 8bit, and the first bit is bit[0]

function [31:0] NextCRC;

input [7:0] D;

input [31:0] C;

reg [31:0] NewCRC;

begin

NewCRC[0] = C[24]^C[30]^D[1]^D[7];

NewCRC[1] = C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];

NewCRC[2] = C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];

NewCRC[3] = C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];

NewCRC[4] = C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];

NewCRC[5] = C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];

NewCRC[6] = C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];

NewCRC[7] = C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];

NewCRC[8] = C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];

NewCRC[9] = C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];

NewCRC[10] = C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];

NewCRC[11] = C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];

NewCRC[12] = C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];

NewCRC[13] = C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];

NewCRC[14] = C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];

NewCRC[15] = C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];

NewCRC[16] = C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];

NewCRC[17] = C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];

NewCRC[18] = C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];

NewCRC[19] = C[11]^C[31]^D[0]^C[27]^D[4];

NewCRC[20] = C[12]^C[28]^D[3];

NewCRC[21] = C[13]^C[29]^D[2];

NewCRC[22] = C[14]^C[24]^D[7];

NewCRC[23] = C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];

NewCRC[24] = C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];

NewCRC[25] = C[17]^C[27]^D[4]^C[26]^D[5];

NewCRC[26] = C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];

NewCRC[27] = C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];

NewCRC[28] = C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];

NewCRC[29] = C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];

NewCRC[30] = C[22]^C[31]^D[0]^C[28]^D[3];

NewCRC[31] = C[23]^C[29]^D[2];

NextCRC = NewCRC;

end

endfunction

//=======================================================================

always @ (posedge clk or posedge rst)

if (rst) crc_reg <= 32'hffffffff;

else if (init) crc_reg <= 32'hffffffff;

else if (data_en) crc_reg <= NextCRC(frame_data,crc_reg);

else if (crc_rd) crc_reg <= {crc_reg[23:0],8'hff};

always @ (crc_rd or crc_reg)

if (crc_rd)

crc_out <= ~{crc_reg[24],crc_reg[25],crc_reg[26],crc_reg[27],crc_reg[28],crc_reg[29],crc_reg[30],crc_reg[31]};

else

crc_out <= 0;

//caculate CRC out length ,4 cycles

//CRC_end aligned to last CRC checksum data

always @(posedge clk or posedge rst)

if (rst) counter <= 0;

else if (!crc_rd) counter <= 0;

else counter <= counter + 1;

always @ (counter)

if (counter == 3) crc_end = 1;

else crc_end = 0;

//=======================================================================

endmodule

互联网MAC层CRC32 生成器

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互联网MAC层CRC32 生成器

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